x86 everywhere?

By , 2006年7月5日 5:32 下午

2006年6月是一个值得嵌入式系统领域深思的月份。这个月的14日,AMD宣布将其Alchemy产品线出售给Raza Microelectronics, Inc.。同月27日,Intel宣布将其XScale产品线以6美元亿的价格出售给Marvell Technology Group,

1995 年DEC从ARM公司(Advanced RISC Machines)获得授权研发生产基于ARM核的处理器,逐步形成自己的StrongARM产品线,主要应用于其网络终端产品中。Intel于1997 年以7亿美元的价格从DEC收购其StrongARM产品线,并将其重新定位于极顶盒、销售终端和手机市场。2003年底,StrongARM技术被 XScale技术所取代。基于XScale技术的PXA系列处理器目前被广泛应用在个人数字助理和智能电话领域。但是,市场上的收入似乎不能够支付该部门 庞大的研发费用,因此Intel最终还是决定将其XScale部门出售,并指出该公司在嵌入式系统领域将集中精力研发更低功耗的x86处理器。

AMD 于2002年收购Alchemy Semicondutor Inc.以获得其MIPS产品线,旨在嵌入式系统领域与Intel的XScale产品线相抗衡。Alchemy公司创立于1999年,提供超低功耗的 MIPS处理器Au1000 (500MHz@1.0W, 400MHz@0.5W)以及基于Au1000的解决方案,目标市场为个人数字助理(PDA)和便携式媒体播放器(PMP)。AMD收购Alchemy之 后,对Au1000处理器的性能和功耗两方面做了大幅度改,于2003年发布Au1100 (400MHz@0.25W),于2005年发布Au1500 (500MHz@0.25W)。值得注意的是,Au1500在不需要外部DSP支持的情况下可以流畅地播放DVD。但是,由于多方面的原因(通常的观点是 AMD并没有投入足够的力量将基于Alchemy的解决方案推向市场),市场上很少见到基于Alchemy系列处理器的消费产品。

值得一 提的是,Alchemy公司的首席技术长官Rich Witek和工程部副总裁Greg Hoeppner均曾在DEC任职,就是他们领导了StrongARM系列产品线的设计工作。他们的团队在研发低功耗高性能的RISC处理器方面赫赫有 名。在Intel从DEC收购StrongARM部门之后,他们决定自立门户但是仍然希望在嵌入式处理器领域有所发展。为了避嫌他们选择了MIPS体系结 构,并利用他们在优化ARM体系结构时候的经验创造了Alchemy系列处理器,因此Alchemy系列处理器又有一个别命叫StrongMIPS。

AMD 出售Alchemy的举动,显然与其雄心勃勃的x86 everywhere计划有关。这一计划说的简单点,就是用x86体系结构征服服务器、个人电脑、嵌入式设备等所有领域,只要是需要计算设备的地方,都为 其提供基于x86体系结构的解决方案。2003年(也就是AMD收购Alchemy的第二年),AMD从国家半导体(National Semicondutor, Inc)收购了其低功耗的Geode产品线,为x86 everywhere计划的实现打下了基础。2005年AMD发布了 Geode LX800处理器,该处理器工作在500 MHz时的平均功耗仅为1.8W,目前已经被广泛应用在瘦客户端领域。盛传Geode LX800这款处理器也就是麻省理工学院的一百美元电脑计划的重要候选者。AMD的目标是进一步降低Geode系列处理器的功耗,使其能够应用在便携式设 备上。从目前的种种迹象来看,AMD很有可能在2008年前后 — 也许会更早 — 发布一款主频在500MHz左右但是平均功耗仅为0.50W的Geode处理器。

与AMD有着类似计划的是VIA(威盛电子),这家在北 京大街小巷到处发布安全套广告(更持久,更安全)的中国芯公司新近发布的VIA C7-M ULV779 1.0GHz 3.5W与AMD的Geode LX800在性能上非常接近,虽然它的主频是Geode LX800的两倍。可以确定的是,VIA仍会不断往降低功耗方面努力,暂时不能够确定的只是VIA将会选择什么时间来发布一款具有震撼力的作品。

下 面列出一些有代表性的x86结构体系的低功耗处理器。如果这些单纯的数字不能够帮助您想象它们的功耗到底有多低,那么请记住主频为3.2 GHz的Intel Xeon E7520处理器的功耗是103W。在这里我只列出了主频和功耗两项参数,熟悉处理器的朋友马上就会指出其实性能才是我们需要的参数,可惜的是我暂时没有 时间去挨个查找所有这些处理器的benchmark数据,所以现在我们只需要记住所有这些处理器在配上512 MB内存的情况下都能够流畅地运行Windows XP Professional版本就可以。

Intel Celeron 815E 400MHz 4.2W
Intel Pentium III 400MHz 10.1W
Intel Pentium M 1.4GHz 10W
AMD Geode LX800 500MHz 1.8W
AMD Geode LX700 433MHz 1.3W
VIA C7-M ULV779 1.0GHz 3.5W
VIA C7-M ULV775 1.5GHz 7.5W

为了了解一下x86与基于RISC的处理器的距离还有多远,下面列出一些有代表性的RISC结构体系的低功耗处理器。同样,这里我暂时只能够给出主频和功耗这两项参数。

AMD Alchemy Au1100 400MHz 0.25W
Intel PXA 270 520MHz 0.7W
Freescale i.MX31 532MHz 0.4W
Godson #1 200MHz 0.4W
Godson #2 500MHz 5.0W

很 显然,对于供电条件良好但是对散热要求比较高的嵌入式应用来说,目前的x86低功耗处理器已经完全能够取代基于RISC的解决方案。例如在工控领域,基于 x86的PC-104结构体系毫无疑问的是首选的方案;在银行领域,我们能够频繁看见NCR自动取款机上丑陋的Windows蓝屏;在瘦客户端领域,基于 RISC的网络终端基本上已经绝迹。但是,对于毫瓦必爭的便携式应用来说,基于x86的解决方案想要赶上基于RISC(主要是ARM)的解决方案,看来还 需要至少三到五年的时间 — 平心而论,这看起来似乎并不遥远。

在这里我也特别列出了龙芯一号和龙芯二号,主要是想看看同在RISC这 个领域我们离世界水平的处理器还有多远。在龙芯的宣传资料中,我们看到了和Petium以及C7的比较,宣称是性能媲美P3全面超过C7 — 在龙芯没有公开发表SPEC数据的情况下,支持或者是反对其说法都没有实质性的意义。然而,龙芯既然是类MIPS的处理器,在目前这种状况下,与x86体 系结构的处理器进行比较,本身就不是十分的合理。就我所知,基于Alchemy Au1100的开发板 — 主要是PB1100和DB1100两个型号 — 在龙芯那里不少,而龙芯的大部分软件应用都是首先在PB1100或者是DB1100上进行开发、移植、测试的。如果龙芯能够公布一些和AMD的 Alchemy Au1100来进行一番比较的话,似乎更能够说明一些问题 。

天黑了,鸟儿都睡觉了,我也先睡了。以后有空再写点。

One Response to “x86 everywhere?”

  1. Charles Xu说道:

    http://findarticles.com/p/articles/mi_m0EKF/is_26_46/ai_63133862

    Embedded Processor Forum 2000 – Product Information
    Electronic News, June 26, 2000 by Tom R. Halfhill
    San JoseaHigh-performance microprocessors and cores for networking, communications and consumer electronics dominated the announcements at the recent Embedded Processor Forum in San Jose. Technical details of more than 20 new products were publicly disclosed for the first time by such vendors as ARC Cores, IBM, Lexra, MIPS Technologies, Motorola and Tensilica. There were also significant announcements in the realm of low-power processors and cores for mobile applications, including 3G cellular phones.

    Five new MIPS-compatible (or MIPS-like) processors and cores were disclosed, more than any other architecture. The most powerful MIPS-compatible embedded core was announced not by MIPS Technologies, but by SiByte, a fabless semiconductor startup. Founded by engineers who designed the high-performance Alpha and StrongARM processors at Digital Semiconductor, SiByte revealed the first technical details of its new SB-1, a 64-bit four-way superscalar core based on the MIPS64 instruction-set architecture. Robert Stepanian, director of architecture at SiByte, says the deeply pipelined SB-1 will deliver more than 2,000 Dhrystone MIPS at a clock speed of 1GHz while consuming only about 2.5Waan extraordinary combination of high performance and low power consumption. The only thing not to like about this core is that it won’t be available for general licensing. SiByte plans to use the SB-1 in a family of integrated network processors scheduled for introduction next year.

    The highest-performance MIPS-compatible embedded processor available for licensing is the new MIPS64 R20K from MIPS Technologies. MIPS also announced the 20Kc, a licensable core for ASIC integration based on the same design. The R20K is a 64-bit two-way superscalar CPU with an FPU, MMU and MIPS-3D graphics extensions. Victor Peng, engineering director of custom CPUs and cores at MIPS, says the R20K will deliver 1,200 Dhrystone MIPS or 2.4 GFLOPS at 600MHz in a 0.18-micron IC process. He expects those numbers to increase by about 25 percent when MIPS ports the core to a 0.15-micron process in 2001. First silicon at 0.18 microns is expected in the third quarter of this year.

    Two other MIPS-based cores were announced by Alchemy, a fabless semiconductor startup, and Lexra, which is not a MIPS licensee. Alchemy, like SiByte, was founded by former Digital engineers who worked on StrongARM. And Alchemy, like SiByte, licensed the MIPS architecture but preferred to design its own CPU core. Alchemy’s Au1000 might be considered a “StrongMIPS” because it brings the same techniques of high-performance and low-power circuit design to the MIPS architecture that StrongARM brought to the ARM architecture. At its peak target clock speed of 500MHz (in a standard 0.18-micron process), the Au1000’s estimated power consumption is only 900mW. At 200MHz, power consumption plunges to 200mW or less. When Alchemy begins shipping Au1000-based chips next year, they should be formidable competitors for Intel’s second-generation StrongARM, which has similar specifications but is due this year.

    Lexra’s MIPS-like NetVortex core is based on the recently introduced LX4189, an R3000-class core, but it adds several features to make it more suitable for high-speed packet processing. The most interesting features are new bit-manipulation instructions not found in the standard MIPS instruction set and up to eight duplicate register files per core. The duplicate registers can hold the state for eight independent threads of execution. Each thread can process a different packet stream, with very fast context switching among threads. Additional features allow ASIC designers to integrate several NetVortex cores on a single chip to handle packet processing at backbone data rates up to OC-192.

    IBM revealed the PowerPC 440GP, the first implementation of its PowerPC 440 core announced at last year’s Embedded Processor Forum. The 440GP uses a 128-bit version of IBM’s on-chip CoreConnect bus to graft an impressive array of peripherals to the superscalar core. Those peripherals include a PCI-X bridge, a 266MHz DDR-SDRAM controller, a 10/100Mbps Ethernet controller and the usual gang of UARTs, I2C interfaces and general-purpose I/O ports. The 440GP will run at 400500MHz in a 0.18-micron copper process, delivering about 720900 Dhrystone MIPS while consuming about 2.43W, according to Donald Senzig, senior PowerPC system engineer at IBM Microelectronics.

    Achieving high performance in an embedded microprocessor is difficult enough, but combining high performance with low power consumption for battery-powered systems is even more challenging. Third-generation cellular phones will need both characteristics. To get there, Motorola disclosed the first details of its integrated chips for 3G wireless handsets. As expected, the chips will unite a 200MHz StarCore SC140 DSP core with a 100MHz M-Core M340 microcontroller and a host of peripherals, including support for USB, IrDA, Bluetooth and multimedia cards (MMCs). Motorola says this combo will be powerful enough to handle all proposed 3G wireless standards, including data-transfer rates ranging from 144Kbit/sec. to 2Mbit/sec. for mobile Internet access. Motorola plans to begin shipping the first chips based on this design next year.
    …….

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